This approach is realized by the combination of dedicated adjustable circuitry and adjustment software, with the values for multiple programmable delay circuits inserted into the clock lines being determined by the adjustment software after fabrication. To solve the problem of fluctuations in clock timing (also known as "clock skew" problems), we propose an approach for the implementation of post-fabrication clock-timing adjustment utilizing genetic algorithms (GAs). This approach could be applied to a wide variety of analog LSIs. However, our technique can improve yield rates of analog LSIs and has two additional advantages, namely, smaller circuits and less power dissipation, which can lead to cost reductions and efficient implementation of analog LSIs.
Analog LSIs with such defective components cannot perform at required levels and thus have to be discarded. When analog Integrated Circuits (ICs) and Large-Scale Integrated Circuits (LSIs) are manufactured, the values of the analog circuit components, such as resistors or capacitors, often vary from the precise design specifications. The developed chip can correct discrepancies in the values of analog circuit components by genetic algorithms (GAs), which have attained (1) a yield rate of 97%, (2) a 60% reduction of the filter area, and (3) a 38% reduction of power dissipation, compared with AKM commercial products. We propose a concept of evolvable analog LSIs and apply it to Intermediate Frequency (IF) filters, which are widely used in cellular phones.